FPGA Boards

RedLinX offers a range of PCIe-based FPGA boards from Netcope Technologies, a leading manufacturer and provider of high-performance network solutions. Netcope excels in packet capture and packet processing technologies and low-latency trading solutions.

TradecopeHardware accelerated, ultra low latency solution for electronic, algorithmic and high frequency trading
NFB-200G2QL200G Ethernet & PCI Express Gen 3 FPGA-based Hardware
NPC-100G2100G Ethernet & PCI Express Gen 3 Packet Capture Solution
NSF-100G2100G Ethernet & PCI Express Gen 3 Session Filter
NDKNetcope Development Kit
Netcope P4Cloud based platform for development of FPGA firmware in P4 language

This is an illustrative sample of the products we have available. Feel free to contact us at sales@redlinx·co·za for information on more options to meet your requirements.

Tradecope: Hardware accelerated, ultra low latency solution for electronic, algorithmic and high frequency trading

The evolution of high-frequency trading together with automated trading systems puts more and more requirements on the trading systems latency. Netcope Technologies offers a solution to minimize latency of trading systems by off-loading the order processing into FPGA hardware.

Tradecope is the first easy-to-use solution for low-latency trading that allows literally everyone to benefit from pure hardware trade processing without the need of being an FPGA expert.

Key features:

  • A-B channel arbitrage
  • Sequence number gap detection
  • FIX/FAST and binary decoding
  • Message and symbol filtering
  • Building an order book representation in FPGA
  • Computation of pre-defined statistics (EMA, MID etc.)
  • Trading strategy triggered by market update
  • Sending orders to market with risk check
  • All data are accessible in software through an API

NFB-200G2QL: 200G Ethernet & PCI Express Gen 3 FPGA-based Hardware

The Netcope FPGA Board NFB-200G2QL is capabile of sending packets to software at line rate of 200 Gbps with zero packet loss by using the latest Xilinx FPGA chip Virtex UltraScale+. The card’s firmware can also effectively distribute traffic to two CPUs in dual-CPU system, bypassing QPI often considered as a bottleneck. The card connects to one or two gen3 x16 PCI-E slots and doesn’t require additional power cables. Last but not least, it comes in a low profile design, so it fits into smaller servers.

Key features:

  • 2 × QSFP28 network interfaces
  • Supported configurations: 2 × 100G / 4 × 50G / 2 × 40G / 8 × 25G / 8 × 10G
  • Ethernet standards:
    • 100GBASE-SR4 (hard IP core for FEC) / LR4
    • 25G / 50GBASE-SR (soft IP cores for FEC)
    • 40GBASE-SR4 / LR4 / IR4
    • 10GBASE-SR / LR
  • PCI Express Gen 3 x16 + x16 (128 + 128Gbps)
  • Xilinx Virtex UltraScale+ chip
  • QDRIIIe SRAM: No QDR / 3 x 72Mb / 3 × 288Mb
  • PPS (pulse per second) time synchronization input
  • Half length & low profile

NPC-100G2: 100G Ethernet & PCI Express Gen 3 Packet Capture Solution

NPC-100G2 is a packet capture solution with two CFP4 or QSFP28 network interfaces. PCI Express Gen 3 x16 host interface allows to transfer the traffic to SW with sustainable throughput of 100Gbps.

NPC firmware provides features for traffic processing at wire-speed. It is possible to preprocess the traffic before forwarding it to SW using hardware filters and intelligent traffic distribution over multiple CPU cores. FPGA technology offers flexibility and possibility of firmware upgrades.

Key features:

  • 2 × CFP4 / QSFP28 network interfaces
    • Each interface supports 1 × 100G / 1 × 40G / 4 × 10G
    • 100GBASE-SR4* / LR4 / ER4
    • 40GBASE-SR4 / IR4 / LR4, 10GBASE-SR / LR
  • PCI Express Gen 3 x16 host interface
  • Aggregate throughput 100Gbps to SW
  • PCI Express form factor
    • Full height (126mm)
    • Half length (180mm)
  • PPS (pulse per second) synchronization input

NSF-100G2: 100G Ethernet & PCI Express Gen 3 Session Filter

The Netcope Session Filter (NSF) is a session-oriented packet capture solution that leverages the hardware platform of Netcope FPGA board to accelerate per-packet processing and flow-based stateful filtering, which leaves more CPU performance for complex processing of network traffic, like DPI. The cooperation of hardware and software makes it possible to build a powerful solution even for 100G Ethernet networks based on commodity multi-core servers.

Key features:

  • 2 × CFP4 / QSFP28 network interfaces
    • Each interface supports 1 × 100G / 1 × 40G / 4 × 10G
    • 100GBASE-SR4* / LR4 / ER4
    • 40GBASE-SR4 / IR4 / LR4, 10GBASE-SR / LR
  • PCI Express Gen 3 x16 host interface
  • Aggregate throughput 100Gbps to SW
  • PCI Express form factor
    • Full height (126mm)
    • Half length (180mm)
  • PPS (pulse per second) synchronization input

NDK: Netcope Development Kit

Netcope Development Kit (NDK) is a development framework that enables rapid development of network applications for FPGA-based cards. The framework creates a hardware-independent abstract layer upon specific hardware cards, solves repetitive tasks of network appliances development such as network and host interface communication, and provides generic interface for the embedded application core.

Key features:

  • Fully synthesizable NDK IP cores
  • NDK simulation model
  • Synthesis and simulation scripts
  • Reference application core
  • FPGA card drivers for Linux OS
  • Command-line tools for Linux OS
  • User, programmer and installation manuals
  • Extended support (optionally)

Netcope P4: Cloud based platform for development of FPGA firmware in P4 language

Netcope chose high-level P4 language as their next-generation means to program Smart NICs. This domain-specific language focused on description of packet forwarding plane is becoming widely supported in network devices. Due to its platform independence, it has never been easier to use the same program on CPUs, NPUs, ASICs or FPGAs.

Using P4 language allows network specialists to benefit from programmable hardware without expert knowledge of FPGAs. Other advantages are full customization of protocol stack to support any encapsulation protocol, possibility of integration of custom accelerators into data path, support of multiple network technologies on a single Smart NIC, etc.

Key features:

  • High-level synthesis based on description in P4
  • Simple web-based user interface
  • Firmware generation in time horizon of hours
  • No need of expert knowledge of FPGA
  • Design can be carried out by a network architect
  • Shorter time-to-market than with HDL
  • Optimized performance to achieve 100Gbps
  • Deployable on Netcope’s Smart NICs
  • Deliverable as IP core
 
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